The image quality of video display systems is constantly increasing. Modern video display systems are capable of creating images having a very large number of intermediate gray-scale light intensity levels. Digital display systems, such as digital micromirror devices (DMD) and some plasma and liquid crystal displays, use pulse width modulation (PWM) to create the appearance of intermediate gray-scale intensity levels even though the display device is actually only capable of creating pixels at full intensity. In other words, PWM allows for the recreation of a wide array of gray-scale intensity levels, even though the actual pixels of the display device are only capable of creating either full light or full darkness levels at a particular time.
A digital micromirror device (DMD), for example, is made up of an array of thousands or even millions of bistable mirror elements, interacting with a light source and a projection surface. Each of the mirror elements of the DMD may switch between two positions, corresponding to an open or closed light configuration, based on the angle at which the mirror tilts towards the light source. A micromirror is in an open position when it is oriented to reflect the light source onto the projection surface. A micromirror is in a closed position when it is oriented so that none of the light provided by the light source is projected onto the projection surface. Thus, each micromirror can be oriented in either an open or “on” position, or a closed or “off” position.
By rapidly turning a particular micromirror “on” and “off”, the appropriate intermediate gray-scale intensity level (shade of light) can be projected for a particular pixel on the projection surface. So a “white” pixel may be produced by having the micromirror remain in the open position for the duration of the frame, a “black” pixel may be produced by having the micromirror remain in the closed position for the duration of the frame, and intermediate shades of gray may be produced by switching the micromirror between the open and closed positions over the course of the frame. The gray-scale shade level of the pixel for a given frame would be proportional to the amount of time that the micromirror was “on,” with the gray-scale shade being darker if the “on” time is less than the “off” time, and the gray-scale shade being lighter if the “on” time is greater than the “off” time for a given frame. Color hues may also be added to a DMD projection system by, for example, time multiplexing the white light source through a color wheel and coordinating the switching of each micromirror with respect to the color wheel in order to blend colors to create the desired hue.
In practice, the micromirrors alternate between open and closed positions so fast that the human eye cannot discern the discrete “on” and “off” positions of each micromirror. Instead, the human eye extrapolates the discrete binary images projected by each mirror element into a wide variety of pixel shades and hues, integrating the pulses of light in a way that produces a perceived flicker-free brightness level. In this way, DMDs allow for the accurate reproduction of a whole array of shades and hues by taking advantage of the human eye's averaging of quickly varying brightnesses and colors.
Generally each micromirror is controlled by a memory cell, typically underlying the micromirror. The pattern of switching a micromirror “on” and “off” to create a particular shade of gray (or hue of color) for a pixel is determined by loading a PWM bit sequence into each memory cell. Creating a very large number of gray-scale intensity levels using a pulse width modulation based system requires short bits; the bit depth of the display device (and thus the number of shades and hues discretely reproducible) depends on the length of the display time period for the least significant bits. As a result, PWM display systems with a high degree of intensity resolution (bit depth) may have some bit display time periods that are shorter than the time required to reload the pixel memory cells. Thus, the physical limitations of the display system (such as the load time and the mirror settling time) may act as a limitation to the available bit depth.
In a DMD, the memory cell under each mirror is generally addressed in a binary fashion according to a PWM sequence, controlling the switching of the micromirror “on” and “off.” For every video frame, each bit-plane of data would first be loaded into the memory cells of the DMD, one bit-plane at a time, and then the bit-plane data in the memory cells under the mirrors would generally be globally applied to all associated mirrors at the same time. This global application of data to all mirrors at the same time is called a “global-reset” operation. As a general rule, a DMD functioning in a global-reset mode loads all memory cells with the entire bit-plane of data before any data may be globally applied to the mirrors.
Using the basic pulse width modulation scheme described above to create intermediate gray-scale intensity levels can introduce image artifacts, however. These sorts of PWM artifacts are recognized in the art and are most visible when there is motion in the image or motion of the viewer's eye and when the image includes adjacent image pixels having intensity levels near, and on either side of, the threshold of the most significant intensity bit.
A number of techniques have been developed to mitigate such PWM artifacts. One technique provides for splitting the duration of the larger bits into multiple, smaller segments and distributing the segments throughout the refresh period. Larger bits, such as the most significant bit, would generally be split into segments that are no smaller than the least significant bit. Using such a bitsplitting technique can create a more pleasing image with less artifacts, serving as an improvement over the more basic PWM sequence (which would leave the mirror in one position for the whole bit period). Problems may arise, however, if the LSB or any bit split segments become too short. If a bit segment display time period is shorter than the load time of the device, then there would not be enough time to load the entire array of memory cells (using a global reset) while quickly turning the short bits “off.” This would act as a physical limitation on the bit depth that the display device might have, limiting the number of intermediate gray-scale intensity levels available for the display device.
A phased reset technique has been developed to attempt to minimize this limitation, allowing shorter display time periods and thus increasing bit depth. Rather than globally applying a bit plane of data to all memory cells (and their associated mirrors) at the same time using a global-reset, a phased reset would load, reset, and display bit plane data in reset groups. Dividing bit planes into reset groups would reduce the amount of data to be loaded at any one time (since only a portion of the bit plane would be loaded into a specific reset group at a time). The accompanying reduction in the load time (for the reset group rather than the entire mirror array) would allow display of smaller bits (with shorter display time periods); unlike global-reset, only the time to load one reset group would limit the display time of the short bit-plane. This phased reset technique, using reset groups, is described in detail in U.S. Pat. No. 6,201,521. While the phased reset technique allows smaller bits and increased bit depth, ultimately the minimum display time period would still be limited by the device's load time for the reset blocks. So again, the load time would serve to physically limit the bit depth of the display device (and if smaller short bits are necessary for image display, then clearing techniques with associated “deadtime” may be required).
Several techniques (for displaying short bits) have been developed to attempt to overcome this limitation on bit depth imposed by the load time (in order to provide shorter display times, allowing a greater number of intermediate gray-scale intensity levels). One example involves the use of “global clear bits.” A global clear function can be performed in a fraction of the load time (for either the entire, global device, or a reset block). In the case of bit-planes representing LSBs with short “on” times, data would be successfully applied to the mirrors and displayed. Then the mirrors would be reset to the “off” state using a global clear function, prior to a new bit-plane being completely loaded into the memory cells of the DMD. This technique may allow for short bits with bit display times less than the load time. The clearing of the entire memory would be needed in order to allow micromirrors to be turned off quickly enough to generate the desired short “on” times (with the micromirrors switching to the “off” position before the next bit-plane has been fully loaded and is ready to be applied). By using a global clear part way through the LSB period, all of the micromirrors of the entire array would be quickly turned off, where they would remain for one split-bit period while the next normal bit-plane (or reset group) finishes loading into the memory cells. The mirrors cannot be turned back on until the DMD is loaded with a new bit-plane (or reset block) of data, resulting in “deadtime” (or an increase in the amount of displayed dark time when the mirrors are in the “off” position) after displaying any LSB bit-planes with display time periods (“on” times) less than the load time (of either the bit plane, if applied globally, or the reset block). The cumulative effect of the “deadtime” that occurs when all of the micromirrors are turned “off” early would be to significantly decrease the display device's brightness.
Similarly, “fast clear bits” may be used to display short bits. A fast clearing technique would insert a fast clear bit within block data loads during a frame refresh period. A short bit would be loaded, but rather than being reset in the normal fashion (which would not be fast enough to display a short bit with a bit display time period less than the load time), the fast clear function would be applied to terminate the short bit at the appropriate time (to provide the short bit display time period). Again, using this technique means that the mirrors would all be turned off (dark) until the next normal load occurs, resulting in “deadtime” and significantly decreasing the brightness of the display device.
So to date, there are several different types of bits that may be used in pulse width modulation. Standard bits are globally applied across all mirrors at the same time using a global-reset operation. Phased reset bits are applied to reset groups, reducing the load time and thereby increasing the bit depth of the device (without resulting in “deadtime”). Clear bits utilize clearing functions to provide for short bits with display time periods less than the load time of either the entire bit-plane or a reset group of the device. So clear bits may be used to increase the available bit depth (by overcoming load time limitations), but this increase in bit depth tends to reduce the brightness of the display device.
Global clear bits and fast clear bits are merely examples of the types of PWM techniques developed to increase bit depth (at the cost of brightness, due to the introduction of “deadtime”). Such short bit techniques may allow for the reproduction of a larger number of intermediate gray-scale light intensity levels. And the shorter bits they enable may help reduce PWM artifacts, especially when used in conjunction with bitsplitting.
Unfortunately, the loss of brightness stemming from the use of various PWM bit sequence techniques designed to allow for increased bit depth may reduce the effectiveness of the overall display device. Thus there is a need for a technique that will allow for increased peak brightness while also allowing for short bit display times, where the memory load (and mirror settling) times exceed the split-bit or LSB display time. Additional details regarding pulse width modulation in general and some of the specific techniques developed to allow for shorter bits (and display time periods less than the load time) may be found in U.S. Pat. Nos. 6,970,150; 6,778,155; and 6,226,054.